In the past, processors (CPUs) were manufactured as a single chip, requiring off-chip access to all their ancillary circuitry, such as memory. As a result, they had a plurality of access pins so that information about the CPU, in particular memory addressing information, was in any event externally available from these access pins.
In addition to memory addressing information, it is useful to be able to obtain status information about the internal state of the processor to ascertain for example such events as interrupts, changes in streams of instructions, setting of flags in various status registers of the CPU, etc.
Nowadays, chips are more complex and contain not only a processor on-chip but also its associated memory and other ancillary circuitry. Often, there may be more than one processor on a chip, or at least one processor and a DMA (Direct Memory Access) engine or EMI (External Memory Interface) for accessing memory associated with the on-chip processor. Thus, it is no longer a simple matter to monitor the operation of the processor because the signals which are normally available off-chip no longer provide a direct indication as to the internal operation of the CPU(s).
With the increasing complexity of software designed to run on integrated circuit CPUs it is increasingly important to adequately test the software. This requires techniques for monitoring operation of the CPU while it executes the software. It is a particularly onerous requirement that the software be monitored non-intrusively while it is operating in real time.
So-called diagnostic or debugging techniques have been developed in an attempt to achieve this. One existing technique (ICE) involves the manufacture of an emulator board which matches the on-chip hardware and which is connected to it. Thus, the on-chip connections are mapped onto the emulator and are thus accessible on the emulator. However, emulators are complex and expensive to construct and in any event cannot successfully match on-chip communication speeds or conditions. Therefore, it is extremely difficult to truly emulate the on-chip conditions which may prevail.
Another existing technique is to use a logic state analyser (LSA). This is a device connected to the pins of the integrated circuit which monitors continuously the state of all off-chip communications. Each sequentially produced set of states is stored and can then be analysed. Not only is an LSA expensive (although it is less expensive than an emulator), but it requires a large amount of deduction and analysis to derive any useful information from the huge number of sequentially produced state sets which are stored. As it is only possible to analyse the status signals being communicated off-chip, it is inevitably necessary to make some deduction or hypothesis concerning the on-chip situations.
More recently, there have been further developments in an attempt to monitor the operations of "embedded" CPUs. In one integrated circuit, a chain of scan latches is implemented on-chip to transfer data from the registers of the CPU using the on-chip TAP controller. The process is destructive and therefore it is necessary to read data back into the CPU registers before the CPU can continue operating. Thus, in order to implement this it is necessary to stop the CPU so that the status information from its registers can be extracted. This does not therefore satisfy the requirement that the software should be monitored in real time. In some cases, halting the CPU can actually change the way in which the software operates so that a bug which is visible in real time would not be evident if the CPU were halted at that point.
Moreover, the monitoring process is slow because it is necessary to wait for a test scan to be completed to allow all of the scan data from the CPU registers to be transmitted off-chip.
It is therefore an object of the present invention to allow improved diagnostic procedures to be implemented by increasing the facility for external communications off-chip.
Various mechanisms exist to allow an off-chip host processor to share information with, control or communicate with an on-chip target processor or other on-chip functionality. However, these mechanisms have drawbacks which mean that they are not particularly suited to real time or non-intrusive diagnostics.
In one architecture, a common memory bus connects off-chip memory and on-chip memory so that these resources can potentially be shared by the host processor and the target processor. However, this requires a large number of connector pins at the chip boundary to effect the bus connections at the boundary.
Moreover, memory arbitration logic is required according to the sharing schemes permitted in the architecture. Buffering is necessary at the chip boundary, and this can compromise performance or latency. Moreover, such an architecture does not allow for non-intrusive diagnostics, because every access is intrusive.
In another architecture, the off-chip host processor communicates directly with the on-chip target processor by a communication line having a small number of connector pins. However, this requires that the on-chip target processor or other functional circuitry has to be increased to handle the communication requirement so that when in use a performance penalty is incurred. Moreover, the host processor can only access the on-chip memory in the address space of the target processor by causing the target processor to effect such a memory access. Thus, any diagnostic procedures involving memory accesses will inevitably be intrusive.
Another known architecture effects communication via UART (Universal Asynchronous Receiver Transmitter). In this architecture, the off-chip host communicates with the on-chip functional circuitry via a serial to parallel converter. Serial to parallel conversion takes place for passing information from the host to the target and parallel to serial conversion takes place in the reverse direction. The connection between the converter and the target is a parallel bus forming part of the on-chip bus system.
Another known architecture provides a serial to parallel converter as an on-chip peripheral with direct memory access (DMA). In this architecture, the off-chip host communicates with the on-chip target via a serial to parallel converter with DMA. Serial to parallel conversion takes place for information passing from the host to the target and parallel to serial conversion takes place in the reverse direction. The connection between the converter and the target is provided by an on-chip bus system. However, it essentially requires a parallel path to allow the on-chip target to control the converter and monitor its status and a path to allow data to be passed in either direction between the host and the memory of the target.
The converter itself does most of the conversion so that the performance of the on-chip target is hardly impacted. However, the on-chip target does have to be involved at the beginning and end of data transfers. At the beginning of a data transfer, the on-chip target controls the converter by enabling it, instructing it where, in memory, to access the information to be communication to the host, how much is being passed and in which direction. At the end of a transfer of data from the host, the on-chip target must act on the supplied data even where it may be a request for information stored in the target memory.
Thus, the input and output of packets necessarily involves the on-chip target.